Column-Parallel Single Slope ADC with Digital Correlated Multiple Sampling for Low Noise CMOS Image Sensors
نویسندگان
چکیده
This paper presents a low noise CMOS image sensor (CIS) using 10/12 bit configurable column-parallel single slope ADCs (SS-ADCs) and digital correlated multiple sampling (CMS). The sensor used is a conventional 4T active pixel with pinned-photodiode as detector. The test sensor has been fabricated in 0.18 μm CMOS image sensor process from TSMC. The ADC nonlinearity measurement result shows totally 0.58% nonlinearity. Using the proposed columnparallel SS-ADC with digital CMS technique, 65% random noise reduction is obtained. The significant noise reduction enhances the sensor’s SNR with 9 dB. © 2011 Published by Elsevier Ltd.
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